Bulletins from the Pacific Packet Radio Society - page 067

chosen by (or forced upon!) the designer lacks the right peripherals. Then there are manufacturers who just make sophisticated peripherals that won't directly interface with anyone's uP -- such parts are called "universal".

It happens that, within TAPR, the majority of the group have a soft spot for the Motorola architecture, and some clever people at Commodore made up a uP that is bus-compatible (that means that the hardware interfaces the same) with the Motorola family (6800,6802,6809) and the uP they made, called a 6502, is very popular. Every Apple, PET, Atari, AIM, KIM and SYM has one. So does the TAPR TNC.

The 6502 family incorporates some powerful peripheral chips, such as the 6551 UART (with baud-rate generator) and the 6522 Parallel Interface (with dual 16-bit timer/counters), both of which are on the TAPR TNC. The family does not include a good HDLC controller (good means on-board PLL for clock recovery from NRZI data as used by nearly every packet group).

Meanwhile, on the other side of the uP architecture, Intel and others have their own families, and were responsible for pushing through a memory standard endorsed by JEDEC (which doesn't necessarily mean much), and many manufacturers have jumped on this band wagon. The concept is called "byte wide", and it makes for a universal socket that can take ROM, EPROM, EEPROM and RAM. It uses a "two-line" control, which is nice for them and bad for the Motorola types. (Heh,heh -- very clever.)

Another outfit, called Western Digital , makes smart peripherals for doing things like HDLC control. Rather than take sides, they use an Intel- like control structure, but invert all the lines so the HDLC chip will need TTL "glue" with everybody's u P. Then they undercut the market with pricing so designers can buy some TTL and still save money!

With this background, the TAPR Hardware group appeased the majority by using the 6502 (in all fairness, a good chip, and one that has a lot of software development behind it within the TAPR infrastructure), the bytewide memory standard and the Western Digital HDLC controller.(For those who may be concerned about the compatibility of the WD 1933 chip with the 8273 used on the Vancouver TNC, let me point out that the KA6M repeater in San Francisco uses the 1933 chip.) As it turns out, the TTL glue needed to tie all of this together, including the clock generator, comes out to four packages, plus a Shottky PROM used for address decoding to allow any mix of RAM/ROM sizes in the bytewide memory area. Alpha TNC's are set for 2 2k-by-8 RAM's and 4 4k-by-8 EPROMS, but the sockets can handle up to 8k-by-8 parts, and the address decoder can be changed very,very easily.

The net result is a TNC that is easily reprogrammable (in a high-level language called FORTH - but that is another issue), capable of using the latest technology in memory components for

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