Bulletins from the Pacific Packet Radio Society - page 173

ROM default at 300 baud, then diddle some parameters (MYCALL, ABAUD, etc), the parameters take fine by throwing S1 and typing RESET. But PERM does not save them, so I have to go thru the 300 baud boot each and every time. Any ideas?

(4) Has anyone got a fix for the reset problem? On power-up the TNC is catatonic until the S3 reset switch is thrown. The 100uf cap should make a clean POC, but doesn't do the trick.

(5) Any ideas when a software patch to solve the PID bug will be issued? Will it necessitate major surgery or can it be easily patched locally. I'd like to get the locals off on the right foot here.

(6) Hank sez that he has TIP/LIP05 for VADG AX.25 in Beta-testing phase now. How soon can we put VADG to rest totally?

(7) For those of you wondering about how wide-spread we are, the AMSAT Beta sites include boards (2 each) for ZS, ZL and JA. Who will get the first packet WAC? I offer the challenge that I currently am leading the WAS tally with 3 (MD,VA,TX). Any challengers? Who (besides N5AHD and I) are set and raring to go on 10 meters?


FILE QST.83.02.2l.0.W4RI

To: Hank Magnuski, KA6M
Lyle Johnson, WA7GXD
Info: Doug Lockhart, VE7APU
From: Paul Rinaldo, W4RI
Subject: Preframe Sync

Thank you, Hank and Doug, for the previous input that you gave me on this subject. I have gone over it several times with Bob Watson with sufficient time for him to reflect on the alternatives.

I told him that of the three protocol controller chips we are using, only the Intel 8273 (not the WD-1933 nor the Zilog 8530) can straightforwardly generate 00 hex or 16-reversal preframe sync. However, all will generate any number of flags. Thus, would a (say) NRZI-encoded two-flag preamble be enough for reliable sync over amateur circuits?

His answer today was "negative." He says that about 10 transitions are needed. That seems to leave us with the following choices:

(1) Forget about requiring any preframe sync.

(I don't like this one at all because we'd have a high probability of miscopying the first few characters until sync is acquired. For less-than-perfect circuits, we can miss the flag

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