Bulletins from the Pacific Packet Radio Society - page 174

without preframe sync because of improper bit timing. The ref ore, not using preframe sync will relegate our protocol chips to operation on only nearly perfect circuits, such as the current 2meter fm packet operations. Taking the 8273 for example, the DPLL will lock immediately on a perfect signal. If there is some noise on the circuit, even at reasonable bit error rates that will let \say) 50% or more of the attempted packets through, the DPLL may require some transitions to achieve optimal timing. The number varies according to where the DPLL initially samples within the RxD data cell. As wars are fought on the edges of two maps, it is possible that, every 32 \first} frames or so, the DPLL could sample on the edge of the data cell. That places the sample at the edge of quadrants Al and A2, which means that the DPLL needs typically 9 counts to move the sample pulse to the center of the data cell. So, we can conclude that depending on S/N and its initial sampling point within the data cell, the chip needs 1 to 9 transitions, to lock its DPLL close enough to the center of the data cell to achieve optimal performance.)

(2) Send an agreed preframe sync pattern.

(The standard would say that the sending station must send the agreed pattern ahead of all packets. That would permit the DPLL to achieve bit synchronization before the flag character is received and thereby minimize the chance of misreading the flag. That would also permit flag recognition even when the SIN is poor - )

(a ) Send 6 preframe flags.

(As each NRZI-encoded flag provides only 2 transitions, about 6 preframe flags are needed to produce the next increment beyond the minimum of 10 transitions. That's 48 bits of overhead! It's not out of the question but is simply inelegant to send 48 bits when only something more than 10 transitions are needed.)

(b) Send 16 reversals.

(This provides more than 10 transitions and does so in only 16 bit intervals, making for low additional overhead.)

Below are choices on how to generate 16 revs:

((1)) Generate it in the TNC/PAD.

(This is possible in the 8273. One can hope that the TAPR TNC TNC with its 1933 and the AMRAD PAD with its 8530 can produce 16 revs with appropriate software.)

((2)) Generate it in the (modem) modulator.

(Sixteen reversals can be generated by one or two chips added to our modulator design which is nearing completion. This seems to be a workable solution for the more difficult circuit applications \satellite, hf and long-haul vhf/uhf } or any time

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